The Symmetrical Cascode OTA

Design

Christian Enz

Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

# Initilization¶

# Introduction¶

Schematic of the symmetrical OTA.

This notebook presents the design of the symmetrical cascode OTA which schematic is shown in the above figure. Note that all nMOS transistors have an odd number and all the pMOS transistors an even number which explains the numbering process. We will design the circuit with M1a-M1b in a separate well.

# Process Parameters¶

All the parameters required for the design are given below. They correspond to a generic $0.18\,\mu m$ process.

    Main physical parameters:
    ═════════════════════════

$T =$ 300 K
$U_T =$ 25.875 mV

    Main process parameters for TSMC 0.18um:
    ════════════════════════════════════════

$V_{DD} =$ 1.8 V
$C_{ox} =$ 8.443 $\frac{{fF}}{{\mu m^2}}$
$W_{min} =$ 200 nm
$L_{min} =$ 180 nm

    nNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.27
$I_{spec\Box} =$ 715 nA
$V_{T0} =$ 455 mV
$L_{sat} =$ 26 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.000 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.200 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 8.1e-24 J
$AF =$ 1.0
$\rho =$ 5.794e-02 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 600 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 39 nm
$\Delta L =$ −76 nm

    pNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.31
$I_{spec\Box} =$ 173 nA
$V_{T0} =$ 445 mV
$L_{sat} =$ 36 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.121 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.248 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 6.8e-23 J
$AF =$ 1.0
$\rho =$ 4.828e-01 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 2386 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 54 nm
$\Delta L =$ −72 nm

# OTA Specifications¶

The OTA specifications are included in the file specs.py. For this design, they are focused on the gain-bandwidth product and dc gain without any constraints on the flicker noise or corner frequency.

$A_{dc} =$ 100 dB
$GBW =$ 1 MHz
$C_L =$ 1 pF
$V_{os,max} =$ 10 mV
$PM =$ 60 degree

# OTA Sizing¶

We need to start with choosing the curent gain $A_3$. We have seen that having a current gain $A_3 > 1$ improves the transconductance but this is at the cost of a higher thermal noise excess factor. We therefore will set $A_1=A_2=A_3=1$

$A_1 =$ 1
$A_2 =$ 1
$A_3 =$ 1

Since $A_1 = A_2 = A_3 = 1$, transistors M2a, M2b, M2c and M2d are all identical and so are M3a and M3b. We therefore have the following variables:

- M1a-M1b: $W_1$, $L_1$ and $I_b$. Note that the current $I_b$ is set by $G_{m1}$ because M1a-M1b are biased in weak inversion,
- M2a-M2c and M2b-M2d: $IC_2$, $W_2$ and $L_2$ since the current is already set,
- M3a-M3b: $IC_3$, $W_3$ and $L_3$ since the current is already set,
- M4: $IC_4$, $W_4$ and $L_4$ since the current is already set,
- M7: $IC_7$, $W_7$ and $L_7$ since the current is already set,
- M5a-M5b: $IC_5$, $W_5$ and $L_5$ since the current is already set.

## Sizing differential pair M1a-M1b¶

In this example there is no specification on the thermal noise. Therefore the transconductance $G_{m1}$ is set by the gain-bandwidth product according to \begin{equation*} GBW = \frac{G_{m1}}{2 \pi C_{out}}, \end{equation*} where $G_{m1}$ is the gate transconductance of M1a and M1b and $C_{out}$ the total output capacitance \begin{equation*} C_{out} = C_o + C_L \end{equation*} with $C_o$ the parasitic capacitance at the output node and $C_L$ the load capacitance.

In order to minimize the input-referred noise and offset, the input differential pair should be biased in weak inversion. The transconductance $G_{m1}$ in weak inversion is then given by \begin{equation*}\ G_{m1} = \frac{I_b}{n U_T}. \end{equation*} The bias current $I_b$ is the current flowing in each transistor M1a and M1b when the input differential voltage is zero. The bias current provided by M5b is therefore $2 I_b$. The bias current must satisfy the following inequality: \begin{equation*} I_b \geq 2\pi n_{0n} U_T C_{out} GBW_{min}. \end{equation*} Neglecting the output parasitic capacitance $C_o$ for now, the minimum bias current to achieve the target GBW is given by

$I_{bmin} =$ 206.694 nA

The corresponding slew-rate is given by

$SR_{min} =$ 206.694 kV/s

which we will consider as sufficient. If this would not be the case we need to increase the current or move to an adaptive OTA.

To have some margin on the $GBW$ to account for the parasitic capacitance at the output $C_o$ that adds to $C_L$ but which we cannot estimate at this point, we set $I_b$ to

$I_b =$ 250 nA

and the inversion coefficient $IC$ to

$IC_1 =$ 0.1

The transconductance can be calculated from the $G_m/I_D$ function as

$G_{m1} =$ 6.962 µA/V

which leads to the following $GBW$

$GBW =$ 1.1 MHz

which is slightly higher than the target specification offering some margin.

Knowing the drain current $I_{D1}$ and the inversion coefficient, we can calculate the $W/L$ aspect ratio for M1a-M1b:

$I_{spec1} =$ 2.5 µA
$\frac{W_1}{L_1} =$ 3.5

Before finalizing the sizing of the differential pair, we first will size the current mirrors.

## Sizing the pMOS current mirrors M2a-M2c and M2b-M2d¶

The drain voltage of M2a and M2b should be set as low as possible for a given maximum common mode input voltage still keeping M1a and M1b in saturation. For a maximum input common-mode voltage $V_{icmax}$ given by

$V_{icmax} =$ 1.3 V

The minimum source-to-gate voltage of M2a-M2b $V_{SG2}$ for this maximum input common mode voltage $V_{icmax}$ is given by \begin{equation*} V_{SG2} = V_{DD} - V_{icmax} + V_{GS1} - V_{DSsat1}. \end{equation*} The gate-to-source voltage $V_{GS1}$ and the saturation voltage $V_{DSsat1}$ of M1a-M1b are given by

$V_{GS1} =$ 382.4 mV
$V_{DSsat1} =$ 104.8 mV
$V_{SG2} =$ 777.6 mV

We set $V_{SG2}$ to

$V_{SG2} =$ 800 mV

This corresponds to an inversion coefficient given by

$IC_2 =$ 24.8

The saturation voltage of M2a-M2d is then given by

$V_{DSsat2} =$ 277 mV

The specific current transconductance and W/L are then given by

$I_{spec2} =$ 10.1 nA
$G_{m2} =$ 1.3 µA/V
$\frac{W_2}{L_2} =$ 5.8e-02

We will now have to make sure that the non-dominant pole $f_{p2}$ and $f_{p4}$ at nodes 2 and 4 are sufficiently higher than the GBW to insure the desired phase margin. The non-dominant pole is given \begin{equation*} \omega_{p2} = \frac{G_{m2}}{C_2}, \end{equation*} where $C_2$ is given by \begin{equation*} C_2 = 2(C_{GS2} + C_{GB2}) \end{equation*} Assuming M2 is in strong inversion and saturation, we have \begin{equation*} C_{GS2} \cong \frac{2}{3}\,W_2\,L_2\,C_{ox} + W_2 \cdot C_{GSOp} \end{equation*} and \begin{equation*} C_{GB2} \cong \frac{n_{0p}-1}{3\,n_{0p}}\,W_2\,L_2\,C_{ox} + W_2 \cdot C_{GBOp}. \end{equation*}

The capacitance at node 2 scales with $W_2$ and $L_2$ according to \begin{equation*} C_2 = W_2\,L_2 \cdot C_{WL} + W_2 \cdot C_W, \end{equation*} with \begin{align*} C_{WL} &= 2\,C_{ox} \left(\frac{2}{3} +\frac{n_{0p}-1}{3\,n_{0p}}\right),\\ C_W &= C_{GSop} + G_{GBop}. \end{align*}

Since the $W/L$ has already been set by the transconductance and the current, we can derive $W_2$ and $L_2$ for achieving a given capacitance $C_2$ according to \begin{align*} W_2 &= \frac{-C_W \cdot W_2/L_2 + \sqrt{W_2/L_2} \cdot \sqrt{4\,C_2\,C_{WL}+C_W^2 \cdot W_2/L_2}}{2\,C_{WL}},\\ L_2 &= \frac{W_2}{W_2/L_2}. \end{align*}

Setting the non-dominant pole $f_{p2}$ to 10 times the $GBW$, we get

$\frac{f_{p2}}{GBW} =$ 10
$C_2 =$ 19.3 fF
$W_2 =$ 300.000 nm
$L_2 =$ 5.140 µm

We choose

$W_2 =$ 300.00 nm
$L_2 =$ 5.14 µm

We can check

$C_2 =$ 19.6 fF
$f_{p2} =$ 10.9 MHz
$\frac{f_{p2}}{GBW} =$ 9.9

Since $A_1=A_3=1$, M2a, M2b, M2c and M2d are all identical and hence

$W_{2a}=W_{2b}=W_{2c}=W_{2d}=$ 300 nm
$L_{2a}=L_{2b}=L_{2c}=L_{2d}=$ 5.14 µm

## Sizing nMOS current mirror M3a and M3b¶

To size M3a and M3b we need to

- consider the output swing and
- make sure that M2c remains in saturation for the chosen overdrive voltage chosen for M3a.

Let's start maximizing the output swing assuming that we bias the cascode transistor M7 in weak inversion for minimum saturation voltage and maximum $G_m/I_D$. We set the inversion coefficient of M7 to

$IC_7 =$ 0.1

The saturation voltage of M7 is then given by

$V_{DSsat7} =$ 105 mV

Let's say that we want an output swing of 1V this means that we have 0.8V to share between the positive and negative saturation voltages which we decide to split equally. This means 0.4V for the saturation voltages of M7 and M3b which leaves a saturation voltage for M3b:

$V_{DSsat3} =$ 295 mV

which gives an inversion coefficient for M3b:

$IC_3 =$ 28.5

which we round to

$IC_3 =$ 28

We now can check whether with the chosen inversion coefficient for M3b, M2c remains in saturation. The $V_{GS3}$ is given by

$IC_3 =$ 28
$V_{GS3a} =$ 824 mV
$V_{SD2c} =$ 976 mV
$V_{DSsat2c} =$ 277 mV

Which is OK.

Knowing the current and the $IC$ we can deduce the $W/L$ as

$I_{spec3} =$ 8.929 nA
$G_{m3} =$ 1.272 µA/V
$\frac{W_3}{L_3} =$ 1.2e-02

Similarly to what was done for transistor M2a-M2c, we need to make sure that the non-dominant pole $f_{p3}$ at node 3 remains much higher than the $GBW$. Setting $f_{p3}/GBW=10$ and proceeding in a similar way we get

$\frac{f_{p3}}{GBW} =$ 10.0
$C_3 =$ 18.3 fF
$W_3 =$ 135.2 nm
$L_3 =$ 10.8 µm

We see that $W_3$ is smaller than the minimum width. If we don't want to increase $W_3\,L_3$ and hence $C_3$, we need to reduce the inversion coefficient $IC_3$. We can find the $IC$ such that $W_3=W_{min}$ for the given $f_{p3}$ in the following way

$IC_3 =$ 16.6
$W_3 =$ 200 nm
$L_3 =$ 9.5 µm
$C_3 =$ 23.7 fF
$f_{p3} =$ 11.1 MHz
$\frac{f_{p3}}{GBW} =$ 10.0

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The inversion coefficient of M3a-M3b is therefore reduced from 28 to 16 in order to maintain a reasonable parasitic capacitance at node 3 to make sure $f_{p3}$ is higher than the $GBW$.

$IC_3 =$ 16.6
$W_3 =$ 200 nm
$L_3 =$ 9.5 µm

M3b is identical to M3a

$W_{3a}=W_{3b}=$ 200 nm
$L_{3a}=L_{3b}=$ 9.5 µm

## Sizing the cascode transistors M4-M7¶

The cascode transistors are sized according to the desired DC gain given by \begin{equation*} A_{dc} = \frac{A_3 \cdot G_{m1}}{G_o} \end{equation*} with \begin{equation*} G_o = \frac{G_{ds3b} \cdot G_{ds7}}{G_{ms7}} + \frac{G_{ds2d} \cdot G_{ds4}}{G_{ms4}} \end{equation*} The DC gain is given by

$A_{dc} =$ 1.0e+05

and the output conductance is then given by

$G_o =$ 69.618 pA/V

We will split the output conductance equally between the NMOS and PMOS cascodes. We already have set the inversion coefficient of M7

$IC_7 =$ 0.1

Knowing the current we can deduce $I_{spec7}$ and $W_7/L_7$ as:

$I_{spec7} =$ 2.5 µA
$\frac{W_7}{L_7} =$ 3.5

Knowing the current and the $IC_7$ we can get $G_{ms7}$ as

$G_{ms7} =$ 8.851 µA/V

We already have chosen the length of M3a and M3b

$L_3 =$ 9.5 µm

The output conductance of M3b can then be estimated as

$G_{ds3} =$ 1.3 nA/V

We can then deduce the output conductance of M7 as

$G_{ds7} =$ 234 nA/V

from which we deduce the length of M7

$L_7 =$ 53.5 nm

which smaller than the minimum length. We choose the minimum length

$L_7 =$ 180 nm
$W_7 =$ 630 nm

The bias voltage $V_{b2}$ has to be set such that M3b remains in saturation. The minimum bias voltage $V_{b2}$ is given by

$V_{DSsat3} =$ 235 mV
$V_{GS7} =$ 455 mV
$V_{b2} =$ 690 mV

For convenience we choose $V_{b2}=V_{DD}/2$.

$V_{b2} =$ 900 mV

M2d has already been sized according to:

$IC_2 =$ 24.8
$L_2 =$ 5 µm
$W_2 =$ 300 nm

The saturation voltage of M2d is then given by

$V_{DSsat2} =$ 277 mV

Similarly for M4 we set the same inversion coefficient as M7

$IC_4 =$ 0.1

from which we get its saturation voltage

$V_{DSsat4} =$ 105 mV

The output swing is then limited to the positive side by

$V_{satp} =$ 382 mV
$V_{DD}-V_{satp} =$ 1.418 V

Knowing the current and the $IC$ we can deduce $I_{spec4}$ and $W_4/L_4$ as

$I_{spec4} =$ 2.5 µA
$\frac{W_4}{L_4} =$ 14.4

The source transconductance of M4 is given by

$G_{ms4} =$ 8.851 µA/V

The output conductance of M2d can be estimated as

$G_{ds2} =$ 2.4 nA/V

We can then deduce the output conductance of M4 as

$G_{ds4} =$ 126.7 nA/V

from which we can calculate the length of M4 as

$L_4 =$ 99 nm

$L_4$ is smaller than $L_{min}$. We choiose $L_4 = L_{min}$

$L_4 =$ 180 nm

From which we get the width of M4

$W_4 =$ 2.60 µm

We finally choose

$W_4 =$ 2.6 µm

The bias voltage $V_{b1}$ has to be set such that M8 remains in saturation. The maximum bias voltage $V_{b1}$ is given by

$V_{DSsat2} =$ 277 mV
$V_{SG4} =$ 445 mV
$V_{b1} =$ 1.1 V

We can set it to $V_{DD}/2$

$V_{b1} =$ 900 mV

We can check the dc gain

$G_{on} =$ 10.336 pA/V
$G_{op} =$ 19.080 pA/V
$G_o =$ 29.416 pA/V
$A_{dc} =$ 2.367e+05
$A_{dc} =$ 107.5 dB

which is within specs.

## Sizing of nMOS current mirror M5a-M5b¶

Finally we need to size M5a-M5b. The saturation voltage of M5b is set by the minimum input common mode voltage

$V_{ic,min} =$ 700 mV

from which we can deduce the maximum saturation voltage of M5b

$V_{GS1} =$ 382 mV
$V_{DSsat5} =$ 318 mV

The corresponding $IC$ is given by

$IC_5 =$ 33.7

We choose

$IC_5 =$ 33

From $I_b$ and $IC_5$ we get $I_{spec5}$ and $W_5/L_5$ as

$I_{spec5} =$ 15.152 nA
$\frac{W_5}{L_5} =$ 2.1e-02

We need to set $W_5$ to the minimum width

$W_5 =$ 200 nm
$L_5 =$ 9.438 µm

We can round $L_5$ to

$L_5 =$ 9.4 µm

Transistor M5a is identical to M5b

$W_{5a}=W_{5b}=$ 200 nm
$L_{5a}=L_{5b}=$ 9.4 µm

## Final sizing of M1a-M1b¶

We haven't finalized the sizing of M1a-M1b. We already have the $W/L$ ratio but still need to set $W_1$ and $L_1$. We don't have any specifications on the noise and particularly the corner frequency, while the white noise is already set by the transconductance $G_{m1}$.

Since the current mirrors current gains are all unity $A_1=A_2=A_3=1$, the transistors M2a, M2b, M2c and M2d are all identical. In this case the contributions of the current mirrors to the input-referred flicker noise relative to the contribution of the differential pair is captured by the $\eta_{fl}$ parameter recalled below \begin{equation*} \eta_{fl} = 1+2\,\frac{\rho_p}{\rho_n} \cdot \left(\frac{G_{m2}}{G_{m1}}\right)^2\,\frac{W_1 L_1}{W_2 L_2} + \left(\frac{G_{m3}}{G_{m1}}\right)^2 \cdot \frac{W_1 L_1}{W_3 L_3}. \end{equation*} The ratio of the flicker noise parameter of pMOS transistors to that of nMOS transistors is given by

$\frac{\rho_p}{\rho_n} =$ 8.333

which is rather large. The square of the transconductance ratio $(G_{m1}/G_{m2})^2$ is given by

$\left(\frac{G_{m1}}{G_{m2}}\right)^2 =$ 26.793

which should compensate for this large $\rho_p/\rho_n$ ratio. We can try to make the contribution of the input differential pair equal to the contribution of the pMOS current mirrors

$W_1 \cdot L_1 =$ 2.309 pm^2
$W_1 =$ 2.8 µm
$L_1 =$ 813 nm

We choose

$W_{1a}=W_{1b}=$ 2.80 µm
$L_{1a}=L_{1b}=$ 810 nm

The contributions to the input-referred flicker noise of the pMOS current mirrors and nMOS current mirror relative to the contribution of the differential pair are given by

    Relative contribution of M2a to M2d = 914.919 m
    Relative contribution of M3a and M3b = 67.211 m

The gamma noise factor and the input-referred white noise are given by

$\eta_{th} =$ 0.782
$\gamma_{ota} =$ 2.3
$R_{ninth} =$ 334.6 kOhm
$S_{ninth} =$ 5.5e-15 $\frac{V^2}{Hz}$
$\sqrt{S_{ninth}} =$ 74.4 $\frac{nV}{\sqrt{Hz}}$
$10 \cdot \log(S_{ninth}) =$ -142.6 $\frac{dBv}{\sqrt{Hz}}$

This sets the corner frequency to

$\eta_{fl} =$ 1.0
$f_k =$ 303 kHz

## Summary¶

### Specifications¶

The specifications are recalled below.

| Name | Value
--- | --- | ---
0 | AdcdB | 1.000000e+02
1 | GBWmin | 1.000000e+06
2 | CL | 1.000000e-12
3 | VDD | 1.800000e+00
4 | Wmin | 2.000000e-07
5 | Lmin | 1.800000e-07
6 | Vosmax | 1.000000e-02
7 | PMdeg | 6.000000e+01

### Bias¶

The bias information are summarized below.

| Name | Value
--- | --- | ---
0 | VDD | 1.800000e+00
1 | VSS | 0.000000e+00
2 | Ib | 2.500000e-07
3 | Vb1 | 9.000000e-01
4 | Vb2 | 9.000000e-01

### Transistor sizes¶

The transistor sizes are summarized below.

| Type | Function | W | L | ID
--- | --- | --- | --- | --- | ---
M1a | n | DP | 2.80E-06 | 8.10E-07 | 2.50E-07
M1b | n | DP | 2.80E-06 | 8.10E-07 | 2.50E-07
M2a | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07
M2b | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07
M2c | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07
M2d | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07
M3a | n | CM | 2.00E-07 | 9.49E-06 | 2.50E-07
M3b | n | CM | 2.00E-07 | 9.49E-06 | 2.50E-07
M4 | p | CA | 2.60E-06 | 1.80E-07 | 2.50E-07
M5a | n | CM | 2.00E-07 | 9.40E-06 | 5.00E-07
M5b | n | CM | 2.00E-07 | 9.40E-06 | 5.00E-07
M7 | n | CA | 6.30E-07 | 1.80E-07 | 2.50E-07

| Type | Function | W | L | ID | W/L | Ispec | IC | VP-VS | VG-VT0 | ... | CGSe | CGDe | CGBe | CBSe | CBDe | CGS | CGD | CGB | CBS | CBD
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
M1a | n | DP | 2.80E-06 | 8.10E-07 | 2.50E-07 | 3.46E+00 | 2.47E-06 | 1.01E-01 | -5.68E-02 | -4.47E-02 | ... | 1.03E-15 | 1.03E-15 | 0.00E+00 | 3.71E-15 | 3.71E-15 | 2.60E-15 | 1.03E-15 | 3.75E-15 | 4.14E-15 | 3.71E-15
M1b | n | DP | 2.80E-06 | 8.10E-07 | 2.50E-07 | 3.46E+00 | 2.47E-06 | 1.01E-01 | -5.68E-02 | -4.47E-02 | ... | 1.03E-15 | 1.03E-15 | 0.00E+00 | 3.71E-15 | 3.71E-15 | 2.60E-15 | 1.03E-15 | 3.75E-15 | 4.14E-15 | 3.71E-15
M2a | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07 | 5.84E-02 | 1.01E-08 | 2.47E+01 | 2.72E-01 | 2.08E-01 | ... | 9.85E-17 | 9.85E-17 | 0.00E+00 | 4.43E-15 | 4.43E-15 | 7.84E-15 | 9.85E-17 | 1.24E-15 | 6.80E-15 | 4.43E-15
M2b | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07 | 5.84E-02 | 1.01E-08 | 2.47E+01 | 2.72E-01 | 2.08E-01 | ... | 9.85E-17 | 9.85E-17 | 0.00E+00 | 4.43E-15 | 4.43E-15 | 7.84E-15 | 9.85E-17 | 1.24E-15 | 6.80E-15 | 4.43E-15
M2c | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07 | 5.84E-02 | 1.01E-08 | 2.47E+01 | 2.72E-01 | 2.08E-01 | ... | 9.85E-17 | 9.85E-17 | 0.00E+00 | 4.43E-15 | 4.43E-15 | 7.84E-15 | 9.85E-17 | 1.24E-15 | 6.80E-15 | 4.43E-15
M2d | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07 | 5.84E-02 | 1.01E-08 | 2.47E+01 | 2.72E-01 | 2.08E-01 | ... | 9.85E-17 | 9.85E-17 | 0.00E+00 | 4.43E-15 | 4.43E-15 | 7.84E-15 | 9.85E-17 | 1.24E-15 | 6.80E-15 | 4.43E-15
M3a | n | CM | 2.00E-07 | 9.49E-06 | 2.50E-07 | 2.11E-02 | 1.51E-08 | 1.66E+01 | 2.20E-01 | 1.73E-01 | ... | 7.33E-17 | 7.33E-17 | 0.00E+00 | 5.77E-15 | 5.77E-15 | 9.34E-15 | 7.33E-17 | 1.44E-15 | 8.29E-15 | 5.77E-15
M3b | n | CM | 2.00E-07 | 9.49E-06 | 2.50E-07 | 2.11E-02 | 1.51E-08 | 1.66E+01 | 2.20E-01 | 1.73E-01 | ... | 7.33E-17 | 7.33E-17 | 0.00E+00 | 5.77E-15 | 5.77E-15 | 9.34E-15 | 7.33E-17 | 1.44E-15 | 8.29E-15 | 5.77E-15
M4 | p | CA | 2.60E-06 | 1.80E-07 | 2.50E-07 | 1.44E+01 | 2.50E-06 | 1.00E-01 | -5.71E-02 | -4.37E-02 | ... | 8.54E-16 | 8.54E-16 | 0.00E+00 | 1.90E-15 | 1.90E-15 | 1.18E-15 | 8.54E-16 | 8.50E-16 | 2.00E-15 | 1.90E-15
M5a | n | CM | 2.00E-07 | 9.40E-06 | 5.00E-07 | 2.13E-02 | 1.52E-08 | 3.29E+01 | 3.15E-01 | 2.48E-01 | ... | 7.33E-17 | 7.33E-17 | 0.00E+00 | 5.72E-15 | 5.72E-15 | 9.67E-15 | 7.33E-17 | 1.34E-15 | 8.33E-15 | 5.72E-15
M5b | n | CM | 2.00E-07 | 9.40E-06 | 5.00E-07 | 2.13E-02 | 1.52E-08 | 3.29E+01 | 3.15E-01 | 2.48E-01 | ... | 7.33E-17 | 7.33E-17 | 0.00E+00 | 5.72E-15 | 5.72E-15 | 9.67E-15 | 7.33E-17 | 1.34E-15 | 8.33E-15 | 5.72E-15
M7 | n | CA | 6.30E-07 | 1.80E-07 | 2.50E-07 | 3.50E+00 | 2.50E-06 | 9.99E-02 | -5.71E-02 | -4.49E-02 | ... | 2.31E-16 | 2.31E-16 | 0.00E+00 | 4.37E-16 | 4.37E-16 | 3.09E-16 | 2.31E-16 | 1.88E-16 | 4.59E-16 | 4.37E-16

12 rows × 32 columns

# OTA Characteristics¶

## Sizing summary¶

### Process parameters¶

    Main physical parameters:
    ═════════════════════════

$T =$ 300 K
$U_T =$ 25.875 mV

    Main process parameters for TSMC 0.18um:
    ════════════════════════════════════════

$V_{DD} =$ 1.8 V
$C_{ox} =$ 8.443 $\frac{{fF}}{{\mu m^2}}$
$W_{min} =$ 200 nm
$L_{min} =$ 180 nm

    nNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.27
$I_{spec\Box} =$ 715 nA
$V_{T0} =$ 455 mV
$L_{sat} =$ 26 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.000 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.200 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 8.1e-24 J
$AF =$ 1.0
$\rho =$ 5.794e-02 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 600 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 39 nm
$\Delta L =$ −76 nm

    pNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.31
$I_{spec\Box} =$ 173 nA
$V_{T0} =$ 445 mV
$L_{sat} =$ 36 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.121 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.248 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 6.8e-23 J
$AF =$ 1.0
$\rho =$ 4.828e-01 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 2386 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 54 nm
$\Delta L =$ −72 nm

### Specifications¶

| Value
--- | ---
Name |
AdcdB | 1.00E+02
GBWmin | 1.00E+06
CL | 1.00E-12
VDD | 1.80E+00
Wmin | 2.00E-07
Lmin | 1.80E-07
Vosmax | 1.00E-02
PMdeg | 6.00E+01

$A_{dc} =$ 100 dB
$GBW =$ 1 MHz
$W_{min} =$ 200 nm
$L_{min} =$ 180 nm
$V_{os,max} =$ 10 mV
$PM =$ 60 deg

### Bias information¶

| Value
--- | ---
Name |
VDD | 1.80E+00
VSS | 0.00E+00
Ib | 2.50E-07
Vb1 | 9.00E-01
Vb2 | 9.00E-01

$I_b =$ 250 nA
$V_{b1} =$ 900 mV
$V_{b2} =$ 900 mV

### Transistors information¶

| Type | Function | W | L | ID | W/L | Ispec | IC | VP-VS | VG-VT0 | ... | CGSe | CGDe | CGBe | CBSe | CBDe | CGS | CGD | CGB | CBS | CBD
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
M1a | n | DP | 2.80E-06 | 8.10E-07 | 2.50E-07 | 3.46E+00 | 2.47E-06 | 1.01E-01 | -5.68E-02 | -4.47E-02 | ... | 1.03E-15 | 1.03E-15 | 0 | 3.71E-15 | 3.71E-15 | 2.60E-15 | 1.03E-15 | 3.75E-15 | 4.14E-15 | 3.71E-15
M1b | n | DP | 2.80E-06 | 8.10E-07 | 2.50E-07 | 3.46E+00 | 2.47E-06 | 1.01E-01 | -5.68E-02 | -4.47E-02 | ... | 1.03E-15 | 1.03E-15 | 0 | 3.71E-15 | 3.71E-15 | 2.60E-15 | 1.03E-15 | 3.75E-15 | 4.14E-15 | 3.71E-15
M2a | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07 | 5.84E-02 | 1.01E-08 | 2.47E+01 | 2.72E-01 | 2.08E-01 | ... | 9.85E-17 | 9.85E-17 | 0 | 4.43E-15 | 4.43E-15 | 7.84E-15 | 9.85E-17 | 1.24E-15 | 6.80E-15 | 4.43E-15
M2b | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07 | 5.84E-02 | 1.01E-08 | 2.47E+01 | 2.72E-01 | 2.08E-01 | ... | 9.85E-17 | 9.85E-17 | 0 | 4.43E-15 | 4.43E-15 | 7.84E-15 | 9.85E-17 | 1.24E-15 | 6.80E-15 | 4.43E-15
M2c | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07 | 5.84E-02 | 1.01E-08 | 2.47E+01 | 2.72E-01 | 2.08E-01 | ... | 9.85E-17 | 9.85E-17 | 0 | 4.43E-15 | 4.43E-15 | 7.84E-15 | 9.85E-17 | 1.24E-15 | 6.80E-15 | 4.43E-15
M2d | p | CM | 3.00E-07 | 5.14E-06 | 2.50E-07 | 5.84E-02 | 1.01E-08 | 2.47E+01 | 2.72E-01 | 2.08E-01 | ... | 9.85E-17 | 9.85E-17 | 0 | 4.43E-15 | 4.43E-15 | 7.84E-15 | 9.85E-17 | 1.24E-15 | 6.80E-15 | 4.43E-15
M3a | n | CM | 2.00E-07 | 9.49E-06 | 2.50E-07 | 2.11E-02 | 1.51E-08 | 1.66E+01 | 2.20E-01 | 1.73E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 5.77E-15 | 5.77E-15 | 9.34E-15 | 7.33E-17 | 1.44E-15 | 8.29E-15 | 5.77E-15
M3b | n | CM | 2.00E-07 | 9.49E-06 | 2.50E-07 | 2.11E-02 | 1.51E-08 | 1.66E+01 | 2.20E-01 | 1.73E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 5.77E-15 | 5.77E-15 | 9.34E-15 | 7.33E-17 | 1.44E-15 | 8.29E-15 | 5.77E-15
M4 | p | CA | 2.60E-06 | 1.80E-07 | 2.50E-07 | 1.44E+01 | 2.50E-06 | 1.00E-01 | -5.71E-02 | -4.37E-02 | ... | 8.54E-16 | 8.54E-16 | 0 | 1.90E-15 | 1.90E-15 | 1.18E-15 | 8.54E-16 | 8.50E-16 | 2.00E-15 | 1.90E-15
M5a | n | CM | 2.00E-07 | 9.40E-06 | 5.00E-07 | 2.13E-02 | 1.52E-08 | 3.29E+01 | 3.15E-01 | 2.48E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 5.72E-15 | 5.72E-15 | 9.67E-15 | 7.33E-17 | 1.34E-15 | 8.33E-15 | 5.72E-15
M5b | n | CM | 2.00E-07 | 9.40E-06 | 5.00E-07 | 2.13E-02 | 1.52E-08 | 3.29E+01 | 3.15E-01 | 2.48E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 5.72E-15 | 5.72E-15 | 9.67E-15 | 7.33E-17 | 1.34E-15 | 8.33E-15 | 5.72E-15
M7 | n | CA | 6.30E-07 | 1.80E-07 | 2.50E-07 | 3.50E+00 | 2.50E-06 | 9.99E-02 | -5.71E-02 | -4.49E-02 | ... | 2.31E-16 | 2.31E-16 | 0 | 4.37E-16 | 4.37E-16 | 3.09E-16 | 2.31E-16 | 1.88E-16 | 4.59E-16 | 4.37E-16

12 rows × 32 columns

## Open-loop gain¶

$A_{dc} =$ 2.365e+05
$A_{dc} =$ 107.5 dB
$f_0 =$ 4.7 Hz
$GBW =$ 1.1 MHz
$f_{p2} =$ 11.8 MHz
$f_{p3} =$ 12.2 MHz
$f_{p4} =$ 11.8 MHz
$GBW =$ 1.000 MHz (from spec)
$GBW =$ 1.103 MHz (estimation)
$GBW =$ 1.095 MHz (theory)
$f_0 =$ 4.666 Hz
$f_{p2} =$ 11.790 MHz

We can plot the magnitude and phase of the open-loop gain.

    PGBW = −97.870 deg
    PM = 82.130 deg

## Input-referred noise¶

We now can estimate the input-referred noise PSD.

$G_{m1} =$ 6.956 µA/V
$G_{m2} =$ 1.345 µA/V
$G_{m3} =$ 1.651 µA/V
$\frac{G_{m1}}{G_{m2}} =$ 5.170
$\frac{G_{m1}}{G_{m3}} =$ 4.213
$\gamma_{n1} =$ 0.7
$\gamma_{n2} =$ 0.8
$\gamma_{n3} =$ 0.8
$\eta_{th} =$ 0.783
$\gamma_{nota} =$ 2.3
$R_{ninth} =$ 335.085 kOhm
$S_{ninth} =$ 5.5e-15 $\frac{V^2}{Hz}$
$\sqrt{S_{ninth}} =$ 74.5 $\frac{nV}{\sqrt{Hz}}$
$10 \cdot \log(S_{ninth}) =$ -142.6 $\frac{dBv}{\sqrt{Hz}}$

We see that the OTA thermal noise excess factor is only slightly larger than that of the differential pair. This is due to the rather large $G_{m1}/G_{m2}$ and $G_{m1}/G_{m3}$ ratios.

We can now compute the input-referred flicker noise and the corner frequency.

$(G_{m1}/G_{m2})^2 =$ 26.732
$(G_{m1}/G_{m3})^2 =$ 17.751
$\rho_p/\rho_n =$ 8.333
$(W_1\,L_1)/(W_2\,L_2) =$ 1.471
$(W_1\,L_1)/(W_3\,L_3) =$ 1.195
$\eta_{fl} =$ 0.984
$f_k =$ 302.5 kHz

We see that the current mirrors contribute about the same than the differential pair.

We can plot the input-referred noise

## Input-referred offset voltage¶

The variance of the input-referred offset for $A_1=A_2=A_3=1$ is given by \begin{equation*} \sigma_{V_{os}}^2 = \sigma_{V_{T1}}^2 \cdot (1 + \xi_{V_T}) + \left(\frac{I_b}{G_{m1}}\right)^2 \cdot \sigma_{\beta 1}^2 \cdot (1 + \xi_{\beta}) \end{equation*} where \begin{align*} \xi_{V_T} &= 2\left(\frac{G_{m2}}{A_1\,G_{m1}}\right)^2 \cdot \left(\frac{A_{VTp}}{A_{VTn}}\right)^2 \cdot \frac{W_1 L_1}{W_2 L_2} + \left(\frac{G_{m3}}{G_{m1}}\right)^2 \cdot \frac{W_1 L_1}{W_3 L_3},\\ \xi_{\beta} &= 2\left(\frac{A_{\beta p}}{A_{\beta n}}\right)^2 \cdot \frac{W_1 L_1}{W_2 L_2} + \frac{1}{A_1^2} \cdot \frac{W_1 L_1}{W_3 L_3}. \end{align*} with \begin{align*} \sigma_{V_{T1}}^2 &= \frac{A_{VTn}^2}{W_1 L_1},\\ \sigma_{V_{T2}}^2 &= \frac{A_{VTp}^2}{W_2 L_2},\\ \sigma_{V_{T3}}^2 &= \frac{A_{VTn}^2}{W_3 L_3}, \end{align*} and \begin{align*} \sigma_{\beta 1}^2 &= \frac{A_{\beta n}^2}{W_1 L_1},\\ \sigma_{\beta 2}^2 &= \frac{A_{\beta p}^2}{W_2 L_2},\\ \sigma_{\beta 3}^2 &= \frac{A_{\beta n}^2}{W_3 L_3}. \end{align*}

$\sigma_{VT1} =$ 3.320 mV
$\sigma_{VT2} =$ 4.027 mV
$\sigma_{VT3} =$ 3.630 mV
$\sigma_{\beta 1} =$ 0.664 %
$\sigma_{\beta 2} =$ 0.805 %
$\sigma_{\beta 3} =$ 0.726 %
$\xi_{VT} =$ 0.177
$\xi_{\beta} =$ 4.137
$\sqrt{\sigma_{VT1}^2\,(1+\xi_{VT})} =$ 3.603 mV
$V_{os} =$ 3.643 mV

We see that the $\beta$-mismatch is negligible and that the input-referred offset voltage is dominated by the contribution of the $V_T$-mismatch from the differential pair.

## Current and power consumption¶

The total current consumption, ignoring the current drawn by M5a, is $I_{tot} = (2+A_1+A_3) \cdot I_b$. Assuming the input differential pait M1a-M1b is biased in weak inversion, the bias current is directly related to the gain-bandwidth product $GBW$ according to \begin{equation*} I_b \cong n U_T \cdot \frac{C_L}{A_3} \cdot GBW. \end{equation*} The total current consumption can then be written as \begin{equation*} I_{tot} \cong \frac{2+A_1+A_3}{A_3} \cdot n U_T \cdot C_L \cdot GBW. \end{equation*} The bias current and the total current are proportional to the gain-bandwidth product $GBW$ and the load capacitance $C_L$. In the case $A_1=A_2=A_3=1$, $I_{tot} \cong 4 \cdot n U_T \cdot C_L \cdot GBW$.

$I_{tot} = 4 \cdot n U_T \cdot C_L \cdot GBW =$ 827 nA
$I_{tot} = 4 \cdot I_b =$ 1 µA

# Conclusion¶

This notebook presented the design of the symmetrical OTA based on the design equations derived in the Analysis Notebook. The design will be checked by simulation in the Verification Notebook.